In recent years, flat-panel display apparatuses whose typical example is a liquid crystal display apparatus (LCD) are widely used in devices, such as a personal computer, a television (TV) and the like, which have display screens. Flat-panel display apparatuses generally have thin thickness, light weights, and low energy consumptions. Among the flat panel display apparatuses, research and development of an active matrix LCD is actively performed because the active matrix LCD can provide an excellent display image, which is not disturbed by a crosstalk between adjacent picture elements.
Generally an active matrix LCD 211, as illustrated in FIG. 6, includes a display panel 212, a signal line driving circuit 214, and a scanning line driving circuit 213. The display panel 212 is provided with (i) plural signal lines SL (SL1 . . . SLn), (ii) plural source lines GL (GL1 . . . GLm), and (iii) a plural number of picture elements 216. The signal line driving circuit 214 is for driving the plural signal lines SL, and the scanning line driving circuit 213 is for driving the plural scanning lines GL.
The signal line driving circuit 214 converts, to a parallel format, image data DT supplied sequentially from outside at every horizontal scanning period. The image for one horizontal picture element array attained by the conversion mentioned above is converted into an analog voltage. Then, the analog voltage is supplied to each of the signal lines SL. The scanning line driving circuit 213 supplies a selection signal voltage so that the plural scanning lines GL are selected sequentially one by one or some at a time during one vertical period.
With reference to FIG. 15, the image data DT is explained as follows. The image data DT is supplied in a form of a video signal under NTSC or the like from an outside tuner 150, a DVD apparatus 151, a VTR apparatus 152 or the like. After the image data DT is converted, by a video source 153, into image data DT and display controlling signals including a clock signal CLK, a synchronized signal SYCN and the like, the image data DT is supplied to the signal line driving circuit 214 of an active matrix LCD 211 through a display controller 215 illustrated in FIG. 6. In FIG. 15, the signal line driving circuit 214 is not illustrated.
The display controller 215 controls the signal line driving circuit 214 and the scanning line driving circuit 213. The display controller 215 supplies the image data DT, a source synchronized signal SSP, and a source clock signal SCK to the signal line driving circuit 214. On the other hand, the display controller 215 supplies a gate synchronized signal GSP and a gate clock signal GCK to the scanning line driving circuit 213. In general, some line memories are provided in the display controller 215. The line memories are used for converting a format of the image data DT from an input format to an output format.
Conventionally, no common use of one type of display controller, i.e. integration of the display controllers has been established which allows one type of display controller to be commonly used for every resolution of display apparatuses (e.g. active matrix LCDs): Display controllers like the display controllers mentioned above have been developed individually according to resolutions of the display apparatuses to which the display controllers are to be provided. This is mainly because the line memory needs different memory capacities depending on the resolutions.
To explain with a specific example, in a case of a display controller for an XGA (extended Graphics Array) (1024×768) display controller, a 1024-word line memory can be used. On the contrary, in a case of a display controller for an HDTV (High Definition Television) (1920×1080), the necessary line memory is a 1920-word line memory, which has substantially two times line memory capacity compared with the line memory used for the display controller for XGA. The display controller is made of an LSI (Large Scale Integration). Because the line memory occupies a large part of a circuit space of the LSI, cost (chip size) of the LSI is determined by the memory capacity of the line memory provided in the display controller.
Accordingly, even if common use of a display controller for every resolution that differ from each other to a large extent is established, there is no cost merit by the common use of the display controller. This is because the display controller for common use should have the memory capacity for the maximum resolution. As the result, at present, the display controllers are developed individually for every resolution and no common use of one type of display controller has been actually developed.
Meanwhile, Japanese Laid-Open Patent Application 211846/1996 (Tokukaihei 8-211846, published on Aug. 20, 1996) discloses a method for reducing the line memory capacity. This method relates to a block driving technique for high resolution display apparatus. In the block driving technique, each horizontal pixel array is divided into N picture element blocks (N is a whole number equal to or larger than 2), and is driven per block. Under the block driving technique, this method is arranged such that data for two pixel elements is inputted and outputted into/from pixel memories at a time, and a picture screen is driven in such a manner that every two source driver units adjacent to each other drives the pixel elements. When this method is applied to the display controller for high resolution display apparatus, reduction in the necessary line memory capacity is possible. As the result, the display controller for the high resolution display apparatus can be used as a display controller for low resolution display apparatus.
However, the technique disclosed in Japanese Laid-Open Patent Application 211846/1996 is arranged such that a data bus is connected to the adjacent source drivers. Accordingly, the application of the technique is limited to a case in which there is one source substrate forming the source driver. The technique is not applicable to a case of a large display panel having plural source substrates, for example, as described in Japanese Laid-Open Patent Application 105131/1998 (Tokukaihei 10-105131, published on Apr. 24, 1998).
With reference to FIGS. 7 through 10, a conventional display apparatus (an active matrix LCD) including a display panel that has plural source substrates is explained. Illustration in figures and explanations of the scanning line driving circuit are omitted for convenience.
A display apparatus using an XGA panel 116 is illustrated in FIG. 7. The display apparatus includes the XGA panel 116, a signal line driving circuit 114, and a display controller 110. The signal line driving circuit 114 drives plural signal lines (not illustrated) of the XGA panel 116. The signal line driving circuit 114 includes respective source substrates 115L and 115R for a left screen and a right screen. The source substrate 115L includes four source drivers SD1 to SD4 and the source substrate 115R includes four source drivers SD5 to SD8.
A display controller 110 includes one input route and two output routes. The image data is inputted sequentially. The input starts from the image data for the left end of the screen on the XGA panel 116. On the other hand, the image data of the left screen 117L and the image data of the right screen 117R are outputted at the same time. In order to rearrange this output image data, the display controller 110 includes a first line memory 112 and a second line memory 113 for two lines. The first line memory 112 and the second line memory 113 are 1024-word line memories for use in the XGA. Moreover, the display controller includes a controller section 110, which is not illustrated. The controller section controls operation of each section in the display controller 110.
FIG. 8 is a timing chart of the display apparatus using the XGA panel 116. In the display controller 110, the image data (in the FIG., IN_DT) DT1, DT2, DT3, . . . , DT1024 inputted through an input section 111 are stored sequentially in order from the image data DT1. The storage into the first line memory 112 is carried out from the left end of the first line memory 112. At the same time, previous-line image data (in the FIG., O_DT_L, O_DE_R) DT1, DT2, DT3, . . . , DT1024 (image data of a previous line) are read sequentially from the left side of the second line memory 113, the image data having been already stored in the second line memory 113. The reading starts from data for a left end of the screen and data for a center of the screen. The signal indicated by DE in the FIG. is a display enabling signal indicating a valid data period for one line. Both of the display enabling signal DE and the clock signal CLK are inputted together with the image data DT through the input section 111.
The image data DT1 for the left end of the screen is first data to be written into the left screen 117L. The image data DT1, DT2, DT3, . . . , DT512 are read sequentially from the image data DT1 for the left end of the screen. The read image data are inputted into four source drivers SD1 to SD4 for driving the left screen 117L, starting from the source driver SD1 located leftmost.
On the other hand, the image data DT 513 for the center of the screen is first image data to be written into the right screen 117R. The image data DT513, DT514, DT515, . . . , DT1024 are read sequentially from the image data DT513 for the center of the screen. The read image data are inputted into four source drivers SD5 to SD8 for driving the right screen 117R in order from the source driver SD5 located leftmost.
An output frequency is a half of an input frequency. Accordingly, when it has been completed to store the image data DT1, DT2, DT3, . . . , DT1024 for one line into, for example, the first line memory 112, the second line memory 113, which is the counter part of the first line memory 112, has been emptied by then. Into this empty second line memory 113, the image data DT1, DT2, DT3, . . . , DT1024 for the next one line are stored sequentially in the same way. At the same time, the image data DT1, DT2, DT3, . . . , DT512 and the image data DT513, DT514, DT515, . . . , DT1024 are read by two routes from the first line memory 112 in the same way as mentioned above.
In this way, the image data writing and reading for every line in order are alternately performed respectively by using the first line memory 112 and the second line memory 113.
FIG. 9 illustrates a display apparatus using a HDTV panel 126. The display includes the HDTV panel 126, a signal line driving circuit 124, and a display controller 120. The signal line driving circuit 124 drives plural signal lines (riot illustrated) of the HDTV panel 126. The signal line driving circuit 124 includes source substrates 125L and 125R respectively for the left screen and the right screen. The source substrate 125L includes seven source drivers SD1 to SD7 and the source substrate 125R includes seven source drivers SD8 to SD14.
The display controller 120 includes two input routes and two output routes. The image data of odd numbered picture element (herein, denoted as “odd image data”) and the image data of even numbered picture element (herein, denoted as “even image data”) are inputted into the HDTV panel 126 at the same time. The input starts from the left end of the screen. On the other hand, the image data on the left screen 127L and the right screen 127R are outputted at the same time. In this case again, in order to rearrange the output image data, a first line memory 122 and a second line memory 123 for two lines are provided. These first line memory 122 and the second line memory 123 are the 1920-word line memories for use in the HDTV. In the case of the HDTV, each of the first line memory 122 and the second line memory 123 is made of two 960-word memories, which are a memory for odd number and a memory for even number, because the odd image data and the even image data are inputted at the same time. The 960-word memories of the first and the second line memories 122 and 123 are memory regions independently controllable.
FIG. 10 is a timing chart of a display apparatus using the HDTV panel 126. The odd image data (in FIG., IN_DT_O) DT1, DT3, DT5, . . . , DT1919 and the even image data (in FIG., IN_DT_E) DT2, DT4, DT6, . . . , DT1920 are inputted into the display controller 120 at the same time through the input section 121. The odd image data and the even image data are sequentially stored into the memory for odd number and the memory for even number in the first line memory 122, from the left side of the odd and even memories. The storing of the image data is performed at timing of the clock signal CLK in such a manner that the image data DT1 and DT2, DT3 and DT4, . . . are inputted respectively in to the odd and even memories in this order. At the same time, the previous-line image data (in FIG., O_DT_L, O_DE_R) DT1, DT2, DT3, . . . , DT1920 are read sequentially from the left end of the second line memory 123, the image data having been already stored in the second line memory 123. The reading starts from data for the left end of the screen and data for the center of the screen at the same time.
The image data DT1 for the left end of the screen is the first image data to be written into the left screen 127L. The reading of the image data is carried out from the memory for odd number and the memory for even number alternately. The image data DT1, DT2, DT3, . . . , DT960 are read sequentially, starting from the image data DT1 from the left end of the screen. The read image data are inputted into seven source drivers SD1 to SD7 in order from the source driver SD1 located leftmost.
On the other hand, the image data DT961 for the center of the screen is the first image data to be written into the right screen 127R. The image data DT961, DT962, DT963, . . . , DT1920 read in order form the image data DT961 for the center of the screen are inputted into seven source drivers SD8 to SD14 for driving the right screen 127R in order from the source driver SD8 located leftmost.
The output frequency in this case is also a half of the input frequency. When it has been completed to store the image data DT1, DT2, DT3, . . . , DT1920 for one line into the first line memory 122, the second line memory 123 has been emptied by then. The image data DT1, DT2, DT3, . . . , DT1920 of the next line are stored sequentially into this empty second line memory in the same manner. At the same time, the image data DT1, DT2, DT3, . . . , DT960 and the image data DT 961, DT962, DT963, . . . , DT1920 are read by two routes from the first line memory 122 in the same manner mentioned above.
In this way, in the same way as in the case of the XGA, the controller section (not illustrated) performs the data conversion process for every line by alternatively reading and storing data respectively from/into the first line memory 122 and the second line memory 123.
However, to develop display controllers for respective resolutions, a large effort and high development cost are required. The development also causes the increase in number of part variations, thereby resulting into increase in management cost, deconcentration of quantity of the display controllers into various types of the display controllers in production of the display apparatus, and the other problems. This results in becoming obstacles to cost reduction. Because of inconvenience caused by the problems mentioned above, there has been still a demand for integration of the display controllers (that is, to establish the common use of one type of the display controller) so that the development of the display controllers for respective resolutions becomes unnecessary.
One method for integrating the display controllers, i.e., developing common use of one type of the display controller device is employing, in the XGA panel 116 for low resolution, the display controller (for HDTV) 120 for high resolution, as illustrated in FIG. 11. However, as mentioned before, there is no cost merit in the integration employing an expensive display controller for high resolution in a low resolution display apparatus.
Moreover, on the contrary to the method mentioned above, the integration, at a first glance, seems possible by using two display controllers (for the XGA) 110 for low resolution in the HDTV panel 126 for high resolution, as illustrated in FIG. 12. However, this cannot be realized for the following reason. That is, although only either odd image data or even image data can be inputted into each of the display controllers 110 for the low resolution, both of the odd image data and the even image data for each screen (the left screen and the right screen) need to be outputted from each of the display controllers 110. However, the display controllers 110 cannot convert the image data into desired output image data because the display controllers 110 are mutually independent and do not have a mechanism to exchange data each other.